Embedded mezzanine capacitor technology for printed wiring boards.(Motorola Labs and Vantico A.G.)(Product Announcement)

Motorola Labs and Vantico A.G. have developed a technology for fabricating embedded capacitors in a "mezzanine" layer of an HDI PWB. When asked to explain the term "mezzanine" in the context of discrete embedded passives, Aroon Tungare said, "We use the term mezzanine to emphasize the fact these capacitors are formed in an intermediate layer between a core layer of a PWB and an HDI layer of a PWB. The capacitor, therefore, does not consume any real estate on the HDI layer-except for a microvia that is dropped to access the top capacitor electrode. Thus, if you consider a 1+2+1 HDI PWB where Layer 1 is the HDI copper layer, and Layer 2 is the Core copper layer, the capacitor would be formed between Layers 1 and 2."

A thin layer of Probelec [TM] CFP (Ceramic Filled Photo-dielectric) is used to form parallel plate capacitor structures. As shown in Figure 1, the capacitors are completely buried under the HDI layer, freeing the HDI layer for circuit routing or for surface mount components. The top electrode of the mezzanine capacitor is accessed through a microvia, as illustrated in Figure 2. Discrete embedded capacitors ranging in value from 1 to 500 pico-farads (pF) can be fabricated with the technology.

Material

Probelec [TM] CFP is a ceramic-filled, positive acting, photo-dielectric whose composition has been engineered for optimal electrical performance (up to Gigahertz frequencies) and robust processing. The effective dielectric constant of Probelec [TM] CFP is approximately 20 at 1.8 GHz. The dielectric thickness, area of capacitor electrodes, and material properties of the dielectric define the value and properties of the embedded capacitor. A capacitance density of 16 pF/[mm.sup.2] is achieved for a dielectric thickness of 12 [mu]m; the dielectric breakdown voltage is in excess of 100 Volts. Figure 3 illustrates the relation between capacitor area and capacitor value, and Figure 4 illustrates the relation between capacitor value and measurement frequency for the embedded mezzanine capacitor structures (Ref. 1).

Fabrication

A novel photo-fabrication process has been devised to produce discrete capacitors with excellent control in x, y, and z dimensions. The Probelec [TM] CFP material (Ref. 2) is applied via vertical roller coating (although other coating techniques can also be used) to a planar copper surface of the core PWB. Why did they select a vertical roller coater to apply the Probelec, as opposed to the traditional Vantico approach of curtain coating or horizontal roller coating? "There are a number of different ways to coat the material," explained Tungare. "Of course, the material needs to be formulated slightly differently for each coating process. In fact, at our laboratories, we developed the process using curtain coating. Vantico also had a formulation optimized at one point for horizontal roller coating."

Since copper features are not yet defined on the core PWB, excellent coating thickness control is achieved. The dielectric is dried, and a copper foil (forming the capacitor top electrodes) is laminated to the dielectric. The top capacitor electrodes are defined via print-and-etch processes, and the positive acting Probelec [TM] CFP is then exposed to UV radiation using the top electrode copper as the mask. The exposed dielectric is then developed, exposing the copper surface on the core PWB. Bottom capacitor electrodes ...