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Cadence Design Systems (555 River Oaks Pkwy., San Jose, CA; Tel: 408/943-1234) and Numerical Technologies Inc. (NumeriTech, 70 W. Plumeria Dr., San Jose, CA; Tel: 408/91910) announced they have entered into a technology licensing relationship that will allow companies to provide electronic design automation (EDA) to address the subwavelength gap.
The companies have signed a multi-year, multimillion dollar agreement wherein Cadence, a leading provider of EDA products and services, will license optical proximity correction (OPC), silicon versus layout (SiVL) verification technology, and silicon visualization capabilities from NumeriTech, the premiere provider of subwavelength design-to-manufacture solutions.
Under the agreement, the two companies will jointly work to embed NumeriTech's silicon-proven technology into Cadence physical design and verification products and flows. Transparent access to OPC and SiVL technology will be a critical capability for Cadence customers as the pressure to handle the challenges posed by subwavelength optics continues to shift from manufacturing to design.
Currently, semiconductor feature sizes that are smaller than 0.2-micron are significantly smaller than the 248-nm wavelength of light that is used to produce them during the optical lithography process. The challenge of producing ICs that contain subwavelength features and produce acceptable yields has driven the adoption of subwavelength technologies such as OPC.
The objective of OPC technology is to improve wafer yield by adding nonprinting corrective features to a photomask to proactively compensate for light distortion created by photolithographic processes, which can lead to image degradation. To ensure that the end silicon will still meet intended performance goals, designers must verify a design against a highly accurate simulation of what would be printed, or the 'virtual silicon image.' In addition, the potentially large number of nonprinting features added to a ...