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Combining general purpose and DSP capabilities within hardware multi-threaded execution infrastructure, Series2 META 32-bit SoC processor IP cores promote optimal processor utilization and tolerance to SoC system latencies. Products deliver ability to respond to external event within one clock cycle while also providing Linux/Android applications processor platforms with coherent caches and MMUs. Other features aid efficient integration with multi-standard communications engines.
META processor family redefines key features and attributes needed for tomorrow's systems on chip
Tokyo, Japan: Imagination Technologies, a leading multimedia chip technologies company, announces the full roadmap for its Series2 generation of META processors, designed for the SoC-centric (System-on-Chip) age of silicon design.
The META family of 32-bit SoC processor IP cores is a unique range of embedded processors that combine both general purpose and DSP capabilities within a hardware multi-threaded execution infrastructure to deliver exceptionally high processor utilisation and tolerance to SoC system latencies while also delivering new levels of real-time response that makes them ideal for SoC applications.
Indeed, the META processors are able to deliver both "hard real time" capabilities - the ability to respond to an external event in a single clock cycle including complete context switch - while also providing excellent Linux or Android applications processor platforms with fully coherent caches and MMUs. The META family stands out as a leading example of next generation SoC embedded processor architecture.
Furthermore, by the addition of features to facilitate highly efficient integration with multi-standard communications engines such as Imagination's ENSIGMA UCC programmable Wi-Fi and demodulation engines, META delivers a new generation of processors …