Silicon trends and limits for advanced microprocessors.

Beyond the physical, chemical, and intellectual limits designers have overcome for the past 25 years may lie the ultimate limit to microprocessor design - money.

Gordon Moore, one of the founders of Intel, first observed in the early 1970s that integrated circuit complexity, as measured by the number of transistors per chip, was increasing at an exponential rate and that this rate had been consistent over many years. He went further to predict that transistor count on leading-edge circuits would double every 18 months until fundamental physical limits were reached. His prediction was remarkably accurate over the past 25 years, and we have yet to reach the fundamental limits of silicon-based technology [ILLUSTRATION FOR FIGURE 1 OMITTED]. The continued increase in transistor count has been achieved through a combination of reduced transistor dimensions along with an increase in chip size.

Reduced transistor dimensions have been possible due to continued improvements in integrated circuit patterning technology and to the excellent scaling properties of metal-oxide-semiconductor (MOS) transistors. Robert Dennard of IBM's T.J. Watson Research Center was the first researcher to propose an effective scaling algorithm for MOS transistors that simultaneously improved density, performance, and power [6]. His scaling theory called for reducing transistor dimensions (such as channel length, channel width, and gate oxide thickness) and power supply, all by a given scale factor S, where S is a value less than 1. The result would be a transistor whose area is reduced by [S.sup.2], whose gate delay (or switching speed) is improved by S, and whose amount of energy used each time a gate switches on or off is reduced by [S.sup.3].

The driving engine behind transistor scaling is the ability to pattern ever-smaller feature sizes. Patterns are printed on integrated circuit wafers by focusing light through masks and onto photosensitive films on the wafer surface. This technique, called optical lithography, has constantly been improved, extending down to dimensions thought impossible by process technologists just a few years ago. To support the transistor density improvements in Figure 1, minimum feature sizes have had to be reduced by [approximately]0.7 x every three years. This has been the rate of improvement in the industry for more than 20 years. New integrated circuit technology generations are often referred to by the minimum feature size used in units of micrometers ([[micro]meter], equivalent to [10.sup.-6]m). Recent examples are the introduction by Intel of the 0.8[[micro]meter] generation in 1989, 0.5[[micro]meter] in 1992, and 0.35[[micro]meter] in 1995. By reducing the wavelength of the exposing light, using better lenses, and improving the photosensitive films, optical lithography is now patterning 0.25[[micro]meter] minimum feature sizes in high-volume production. This process is extendible to the 0.18[[micro]meter] generation, which will be used to make Intel's Merced microprocessor in 1999, and beyond that to the 0.13[[micro]meter]-generation.

New-generation process technologies generally come out every three years and provide roughly a 0.7x reduction in minimum feature size. Using 0.7x as the scale factor S, turning of the generations gives a transistor area improvement of 0.49x, a gate delay improvement of 0.7x, and an energy reduction of 0.34x for every new process generation. Figure 2 shows how transistor parameters have scaled over the last six generations of Intel microprocessor technology. Minimum feature size and gate oxide thickness ([T.sub.OX]) have been scaled down by [approximately]0.7x with every generation, while supply voltage ([V.sub.DD]) has been scaled down only for the last three generations. Until the 0.8[[micro]meter] generation, 5V was the industry standard supply voltage; power and reliability were not yet significant enough concerns to justify deviating from the standard supply voltage. But beginning with the 0.5[[micro]meter] generation, chip power and gate oxide reliability concerns forced adoption of scaled supply voltages with every new generation. Throughout this period, transistor performance, measured by inverter circuit …