MAGMA DEBUTS TALUS 1.1 FOR ENHANCED DESIGNER PRODUCTIVIY.

Magma(r) Design Automation Inc. (Nasdaq:LAVA), San Jose, Calif., a provider of chip design software, has released Talus(r) 1.1, a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs. Talus 1.1 utilizes the new Talus(r) COre(tm) technology, which leverages Magma's unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability. This greatly enhances designers' ability to achieve optimal results across a wide variety of designs -- while minimizing the need for user intervention. Unlike existing routing systems that perform optimization sequentially before and after place and route, and which focus only on layout-oriented routing factors such as design for manufacturability (DFM) or design rule checking (DRC), Talus focuses concurrently on timing and layout-driven metrics during routing.

In addition to its ability to provide the fastest turnaround on large designs, Talus 1.1 introduces the Talus(r) Flow Manager(tm) with "out-of-the-box" design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design -- engineers can easily tune the reference flows for specific applications. Talus Flow Manager also introduces a new visual analysis environment, Talus(r) Visual Volcano(tm), that integrates and presents all design and analysis data via a common display.

"For engineers creating ICs at advanced geometries, big chips, or chips where power management is important, Talus is superior to design systems from other EDA vendors," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The first breakthrough at Magma occurred when we added concurrent optimization to placement in our initial product, Blast Fusion. Our new Talus COre technology raises the bar by adding concurrent optimization to routing, resulting in faster design closure and better timing performance. Unlike other approaches, Talus delivers a level of design speed and efficiency that is ideal for small-geometry designs -- this also makes it ideal for designers creating big chips, those with 5 million gates or more. This will take on greater commercial significance for our customers as an increased portion of their designs target applications such as netbooks, smartphones and embedded devices that require bigger and more complex chips but also must be designed for low power."

Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nm, and is presently ready for designs at 32 nm and 28 nm. Such technology is commonly found in System-on-a-Chip (SoC) designs, which integrate computing capabilities on a single chip.

Talus COre Technology

The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal solution with unpredictable results. Traditional solutions must spend ...