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Ensuring the reliability of Electronic Circuits has always been a challenge. As the complexity of systems increases the inclusion of reliability measures becomes progressively more complex and often a necessity for VLSI circuits where a single error could potentially render an entire system useless.
The Evolvable Fault Tolerant system (1) is designed (1) to provide fault tolerant design automatically and (2) to ensure autonomous functional recovery for these devices after an occurrence of unavoidable damage caused by extreme radiation, temperature or simple malfunctions (e.g. severe electric transients, etc).
The way this research investigates faults differs from the conventional way of Fault Tolerance mentioned above. In this research, we will be interested in faults that can occur within the VRC, instead of focusing on environmental problems such as temperature, extreme radiation, etc. The role of fault tolerance is to deal with errors, caused by faults, before they lead to failure. This research describes about the logic simulation tool used to perform the fault simulation. AUSIM: Auburn University SIMulator was very useful in testing the architecture of Virtual Reconfigurable Circuit. It aids in debugging a circuit or in analyzing a circuit in terms of area and performance metrics. The Hardware Description Language (HDL) for AUSIM is Auburn SimulationLanguage (ASL).
VIRTUAL CONFIGURABLE CIRCUIT
The fault Tolerant System is evolved using the idea of VRC on FPGA (2). when the VRC is uploaded in to the FPGA then its configuration bit stream determines Processing Elements (PEs) function and the places where its inputs are connected. The main advantage is that the array of PEs, the routing circuits and the configuration memory can be designed exactly according to the requirements of a given application.
VRCs require more recourses than the other common approaches used to implement a given function in an FPGA, it is realistic to suppose that their use will yield less reliable solutions. Implementation of a circuit costs a few equivalent gates in an FPGA. However, several hundred gates have to be activated if a VRC is utilized. The Pessimistic scenario says that the reliability will be …