DDR1/2 Memory Interface supports TSMC's 90 nm process.(ARM Announces First Production-Ready DDR1 and DDR2 Memory Interface IP on TSMC 90-Nanometer Process)

ARM[R] Velocity(TM) DDR1 and DDR2 memory interface includes multiple sets of programmable on-die termination and output driver impedance control, with all terminations capable of achieving optimal impedance accuracy using ARM advanced dynamic calibrator circuits. Used for scaling power and performance in applications needing SDRAMs, interface operates at up to 800 Mbps and implements complete interface between SDRAM component and memory controller.

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Velocity DDR Memory Interface Attains TSMC IP Quality Certification

CAMBRIDGE, England, December 19 -- ARM [(LSE:ARM; Nasdaq:ARMHY)] today announced the availability of the ARM(R) …