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Technology diversity.(EDITORIAL)
August 1, 2008... Scientific competition among companies has produced numerous solutions to the common problems of the semiconductor industry. That diversity of technical approaches has been built into the very DNA of the industry, resulting in the flexibility...
Accelerating both sparse and dense OPC computation.(Optical proximity correction )
August 1, 2008... Different layers of chips at and below 45nm have different optimal OPC strategies. Some are best served using sparse simulation, while others benefit from dense simulation with a co-processor enhanced server farm. A new type of compute platform...
Extending lithography to the wafer's edge: edge bead removal processes must now tailor and inspect the edges of each layer of an immersion resist stack within the bevel at the very edge of the wafer to prevent catastrophic particle production and transport.
August 1, 2008... A number of manufacturers are actively developing back rinse processes for edge bead removal (EBR), allowing them to extend lithography films into the upper bevel at the wafer edge. In addition to increasing the usable surface area of the...
Measuring line edge roughness: fluctuations in uncertainty.(The Lithography Expert)
August 1, 2008... Line edge roughness (LER) is the deviation of a feature edge (as viewed top-down) from a smooth, ideal shape--that is, the edge deviations of a feature that occur on a dimensional scale smaller than the resolution limit of the imaging tool that...
Automating the CD-SEM recipe process for 45nm technologies: an offline recipe creation process accelerates the monitoring of hotspots in volume manufacturing at the 45nm node.
August 1, 2008... The semiconductor industry is extending 193nm lithography using immersion technology in conjunction with highly restrictive design rules to successfully fabricate devices at the 45nm technology node. Unintended imperfections on the wafer due to...